With recent advancement of digital technologies, electronic hardware such as portable information apparatuses and home information appliances have been developed to provide higher functionality. For this reason, there have been increasing demands for a larger capacity of nonvolatile memory elements, reduction in a write electric power in the memory elements, reduction in write/read time in the memory elements, and longer life of the memory elements.
Under the circumstances in which there are such demands, miniaturization of the existing flash memory using a floating gate has been progressing. In addition to this, a nonvolatile semiconductor memory element (resistance variable memory) including as a memory section a resistance variable element which changes resistance values to be retained stably, in response to voltage pulses applied, is expected to achieve further miniaturization, higher speed, and lower electric power consumption, because a memory cell is allowed to have a simple structure.
Therefore, conventionally, memory cells are each configured to include one transistor and one memory element and perform a stable memory operation, and are highly integrated.
For example, there is disclosed so-called 1T1R-type memory cells each including one transistor and one resistance variable element as a memory cell, in which the resistance variable element includes a resistance variable layer which is located immediately below an upper electrode and comprises a perovskite structure material such that the resistance variable layer has a resistance changing region in a part thereof (see for example patent document 1). The resistance variable element has a structure in which a portion of the lower electrode which contacts a portion of the resistance variable layer is different in area from a portion of the upper electrode which contacts a portion of the resistance variable layer, and the resistance changing region is located immediately on the lower electrode with a smaller area. Therefore, resistance change is allowed to surely occur in a region in the vicinity of the electrode connected to the resistance variable layer with a smaller area, by applying voltages lower than those conventionally used, which enables achievement of miniaturization and reduction of electric power consumption.
An exemplary configuration of 1T1C-type memory cells each including one transistor and one ferroelectric capacitor has been proposed, in which a part of a capacitive insulating layer and a part of upper electrodes do not suffer from damage which would be caused by, for example, exposure to hydrogen gas and the like, during other process steps after manufacturing process steps for forming the capacitive insulating layer comprising ferroelectric capacitors immediately below the upper electrodes (for example, see patent document 2).
An exemplary configuration of 1T1C-type memory cells each including one transistor and one ferroelectric capacitor has been proposed, in which a charging damage to the ferroelectric capacitors can be avoided, because the memory cells have a wire structure in which wires electrically connected to the ferroelectric capacitors are formed by processing a wire material after stacking the wire material on the ferroelectric capacitors (for example, see patent document 3).    Patent document 1: Japanese Laid-Open Patent Application Publication No. 2006-120701    Patent document 2: Japanese Laid-Open Patent Application Publication No. 2006-270116    Patent document 3: Japanese Laid-Open Patent Application Publication No. 2007-95898